What is an L 2 space

Cache (L1 / L2 / L3)

The cache is a special buffer memory that lies between the main memory and the processor.
So that the processor does not have to fetch each program command individually from the slow main memory, an entire command or data block is loaded from the main memory into the cache. The probability that the following program instructions are in the cache is relatively high. Only when all program commands have been processed or a jump command leads to a jump address outside the cache does the processor have to access the main memory again. The cache should therefore be as large as possible so that the processor can execute the program commands one after the other without waiting.

As a rule, processors work with multi-level caches that are of different sizes and speeds. The closer the cache is to the computing core, the smaller and faster it works.

L1 cache / first level cache

The L1 cache is usually not very large. For reasons of space, it is in the order of 16 to 64 kByte. Most of the time, the memory area for commands and data is separated from one another. The importance of the L1 cache grows with the higher speed of the CPU.
The most frequently required commands and data are temporarily stored in the L1 cache so that as few accesses as possible to the slow main memory are required. This cache avoids delays in data transmission and helps to utilize the CPU optimally.

L2 cache / second level cache

The main memory (RAM) data is temporarily stored in the L2 cache.
The processor manufacturers supply the various market segments with specially modified processors via the size of the L2 cache. The choice between a processor with a higher clock speed or a larger L2 cache can be answered in a simplified manner as follows: Individual programs run faster with a higher clock speed, especially those with high computing requirements. As soon as several programs are running at the same time, a larger cache is an advantage. As a rule, normal desktop computers are better served with a processor that has a large cache than with a processor that has a high clock speed.
When the memory controller was moved from the chipset to the processor and the processor was able to access the main memory much faster, the importance of the L2 cache decreased. While the size of the L2 cache has decreased, the L3 cache has been properly upgraded.

L3 cache / third level cache

As a rule, multicore processors use an integrated L3 cache. With the L3 cache, the cache coherence protocol of multicore processors can work much faster. This protocol compares the caches of all cores so that the data consistency is maintained. The L3 cache has less of the function of a cache, but is intended to simplify and accelerate the cache coherence protocol and the data exchange between the cores.

Inclusive cache and exclusive cache

With the multicore processors, the terms inclusive and exclusive cache came up. Inclusive cache means that data in the L1 cache is also available in the L2 and L3 cache. This makes it easier to ensure data consistency between the cores. Compared to the exclusive cache, some storage capacity is wasted because the data is redundantly stored in the caches of several CPU cores.
Exclusive cache means that the cache is available to a processor core exclusively, i.e. for it alone. It doesn't have to share the cache with another core. A disadvantage of this is that several processor cores can only exchange data with one another in a detour.


This is the procedure in which the second-level cache writes the data to the main memory immediately. The cache takes control of the write process. The processor can continue to work during this time.


This is the method in which the second-level cache informs the processor that the data has been written to the main memory.

Write allocation

Write-Allocation is a cache management strategy. When writing to addresses that are not in the cache, this results in the data being read into the cache first. The write process then only takes place on the cache.
Write allocation must be activated in the BIOS.

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