What is DFT design for testability

The introduction of Design-for-Manufacturing (DfM) together with the use of high-quality assembly and testing equipment minimizes the likelihood of assembly errors. Even so, however, assembly errors do occur and PCBAs must be tested to detect these errors in order to achieve PCBAs with zero errors. A test sequence (also known as TestPlan) is used to carry out individual actions (step types) such as power switching, structural or functional tests, limit value comparisons or block programming actions in a logical sequence.


Various parameters determine the type of test and programming hardware that is best suited. These parameters include e.g. performance, form factor, integration options with other test stations that are already in use, etc. In production, a whole range of different modules and module types must be supported when programming modules as part of the circuit board configuration. For reasons of efficiency, such programming should ideally be carried out with the same hardware that is also used for the test.


Design-for-Test (DFT) rules are used to optimize the test process for the detection of manufacturing defects. Modern designs rely on JTAG Boundary-Scan for testing. Boundary scan in one component enables access to your pins regardless of the housing and leads to maximum fault coverage. With our testability analysis, you can determine what percentage of a design can be tested with boundary scan. Our brochure “Board DFT Guidelines” helps you to optimize the boundary scan testability in your design.


Various tests are being developed to achieve maximum fault coverage. Boundary scan tests such as interconnect tests, pull-up / down resistance tests, memory and cluster tests of various logic modules can be generated automatically with ProVision. With the powerful high-level language Python, those parts of the circuit can be tested that cannot be covered by automatic test generators, e.g. sequential circuits, ADCs and DACs.
Regardless of whether your design consists of a single board or multiple assemblies, ProVision covers the different configurations. Once a set of tests has been created, the coverage of those tests can be calculated and compared to the testability of the design to see if additional testing is required. Finally, test sequencing (AEX sequencer) makes running the tests a simple push of a button. The possibility of combining the various tests in a sequence completes the ProVision development environment.


The test sequence is carried out at runtime in order to test the entire assembly. The runtime solutions from JTAG Technologies can be used on their own (stand-alone) or as part of your overall test strategy (JTAG Inside). Production integration packages are available for LabVIEW, LabWindows, TestStand, C, C ++, C #, .NET, Visual Basic and ATEasy. Certified packages (Symphony products) are also available for in-circuit and flying probe testers from Agilent, Teradyne, Digitaltest, Seica, Spea, Cobham, Takaya, etc.


The diagnostic software analyzes the detected errors and reports the cause of the error as well as the networks and pins involved. Visualizer can highlight the location of a fault in the layout and schematic, which makes it easy for factory repair technicians to locate the fault on the building group.

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The programming of blocks takes place within the framework of the assembly configuration. The available programming solutions differ depending on the block type:

  • Flash memory (NOR, NAND, serial)
  • Microcontrollers and DSPs (Embedded Flash)
  • PMBus blocks

Depending on the block type, the programming application can either be generated automatically or provided as ready-made solutions (R2R). The programming applications can be executed with the runtime packages from JTAG Technologies either independently (stand-alone) or integrated into other (test) systems.


Flash memories can be programmed via the boundary scan registers of JTAG modules, which are connected to the address, data and control lines of the flash. In a boundary scan flash programming application, the networks connected to the flash are controlled via the boundary scan registers in order to send data and commands to the flash memory. The applications for flash programming can be created automatically by ProVision, for which there is an extensive library. Alternatively, it is also possible to use the debug logic of a microprocessor to program flash memories that are connected to a processor.


Programming the embedded flash of a microcontroller requires a special solution. JTAG Technologies offers programming solutions for a wide range of microcontrollers (see listing below). These solutions are provided as Ready-to-Run (R2R) programming applications for direct execution with the runtime packages from JTAG Technologies.


Various data formats are supported for in-system programming of FPGAs and CPLDs (SVF, JAM, STAPL and ISC IEEE 1532). PLD programming applications in ISC IEEE 1532 format can be generated automatically with ProVision. SVF, JAM and STAPL files can be executed directly with the respective runtime packages from JTAG Technologies.


Power management modules with the PMBus protocol can be programmed via the boundary scan register of a connected module. In a boundary-scan PMBus programming application, a boundary-scan component acts as a PMBus master to send data to the PMBus component. The applications can be generated automatically with ProVision.


Boundary-scan hardware

To test a module and program blocks, you need the following hardware:

  • A JTAG controller that connects your PC to the JTAG interface of the device under test.
  • I / O modules for boundary scan access via connectors and test points on the assembly.

JTAG controllers

In order to run your test and programming applications reliably, you can choose from a number of different controllers with different performance features and form factors. The controllers of the high-speed DataBlaster JT 37 × 7 series are the top models. They have a scalable performance and are available in different versions.

The mixed-signal controller JT 5705 supports the control and measurement of analog signals in combination with boundary scan. ER is the ideal choice when the focus is not on maximum speed but on flexibility.

I / O modules

If external access for test and analog measurements is required in parts of your design that do not have boundary scan access, there are a number of I / O modules, such as DIOS (Digital I / O Scan), MIOS (Mixed I / O Scan) or socket test (ST) to check sockets, plugs, sensors etc. to test.


Boundary scan controllers and I / O modules are available separately or can be combined in one instrument. The Rack-Mountable Instrument (RMIc), for example, is a stand-alone unit with one or more boundary scan controllers and I / O modules of your choice. Perfect for installation in a 19-inch test rack or as a table system. The JT 5705 effectively combines a 2 TAP controller and mixed IO channels and is therefore an independent ATE.


The high-speed DataBlaster controller series is available in all common formats (PCI, PCIe, PXI, PXI, PXIe, USB, Ethernet, Firewire) and can be integrated into an existing test system as a stand-alone device. Special form factors that are tailored to your tester are also available for seamless integration with your in-circuit tester or flying probe tester.

When JTAG Boundary-Scan is combined with your in-circuit tester, flying probe system or functional tester, you can use the test and measurement hardware of this system. This enables measurements on I / O plugs and test points through the combination with boundary scan.

With our JTAG TapCommunicator there is a product that enables remote access over any distance. The TapCommunicator is a truly unique product that can overcome problems when the device under test is out of reach. By using the native protocol (e.g. E-Net, Bluetooth, SpaceWire etc.) to communicate with the target assembly, boundary scan tests and programming applications can be used over almost any distance.

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